The present invention relates to a semiconductor integrated circuit device in which a plurality of semiconductor chips are integrally encapsulated and a fabricating method thereof.
In recent years, for the achievement of high-density packaging of electronic components, a semiconductor integrated circuit device provided with semiconductor chips 107 and 108 mounted on both surfaces of a die pad 111 formed in a lead frame 110 as shown in FIG. 10 has been proposed (Japanese Utility Model Laid-Open Publication No. SHO 62-147360). This semiconductor integrated circuit device is constructed by bonding (die bonding) the semiconductor chip 107 by means of a silver paste 102 onto one surface 111a of the die pad 111, bonding the semiconductor chip 108 onto the other surface 111b of the die pad 111 by means of a silver paste 103, connecting (wire bonding) electrode pads 107p and 108p formed on the surfaces 107a and 108a of the semiconductor chips 107 and 108 to inner leads 112 and 112 formed in the lead frame 110 by way of respective wires (thin wires such as gold wires) 150 and 150 and thereafter encapsulating (molding) these members in an encapsulating resin 160. It is to be noted that support leads (not shown) formed in the lead frame 110 are cut, and outer leads 113 connected to the inner leads 112 are bent in a shape corresponding to the use. The silver pastes (having epoxy resin blended with silver powder as its main ingredient) 102 and 103 are fluid materials containing a solvent before being hardened, and they are to be hardened by vaporizing the solvent by heating. In a die bonding stage, for example, the silver paste 102 before being hardened is supplied onto the one surface 111a of the die pad 111 and the semiconductor chip 107 is mounted on it, where the silver paste 102 is spread in a planar direction as interposed between the die pad 111 and the semiconductor chip 107. Subsequently, the silver paste 102 is hardened by heating. The reason why the silver paste 102 is spread in the planar direction is for the purpose of preventing the possible occurrence of a cavity which will cause a crack in the encapsulating resin 160 between the silver paste 102 and the semiconductor chip 107.
However, according to the structure shown in FIG. 10, the rear surface 107b of the semiconductor chip 107 is electrically continued to the rear surface 108b of the semiconductor chip 108 via the silver paste 102, the die pad 111 and the silver paste 103. Therefore, the semiconductor chips which can be mounted are limited to those whose rear surfaces (often exposed surfaces of the silicon substrates) 107b and 108b become equi-potential (memory IC chips such as flash memories, mask ROMs and the like fabricated through an identical process). This is because the semiconductor chips do not operate correctly when a semiconductor chip having a P-type silicon substrate and a semiconductor chip having an N-type silicon substrate are mounted or when the electric potentials of silicon substrates are different from each other even if the silicon substrates are of the same type.
In this case, it seems that, if non-conductive silverless pastes (having epoxy resin blended with no silver powder as a main ingredient) 104 and 105 shown in FIG. 11 are used in place of the conductive silver pastes 102 and 103, then the die pad 111 and the rear surfaces 107b and 108b of the semiconductor chips 107 and 108 can be electrically insulated from each other. However, the silverless pastes 104 and 105 are also fluid materials containing a solvent before being hardened similarly to the silver pastes 102 and 103. Therefore, when, for example, the silverless paste 104 is spread in the planar direction as interposed between the die pad 111 and the semiconductor chip 107 in the die bonding stage, the parallelism and distance between the die pad 111 and the semiconductor chip 107 are out of control, possibly leading to a continuity as a consequence of the contact of the semiconductor chip 107 with the die pad 111. The same thing can be said for the semiconductor chip 108. In particular, when an attempt at providing a thin type structure such as TSOP (Thin Small Outline Package) or TQFP (Thin Quad Flat Package) is made, the silverless pastes 104 and 105 cannot help having extremely reduced thicknesses since the semiconductor chips 107 and 108 are stacked in the direction of thickness in the above structure, and this increases the possibility of the contact between the die pad 111 and the semiconductor chips 107 and 108.